1. Technical Field
The present invention relates to a semiconductor device and a method of fabricating the same.
2. Related Art
Double-diffusion field effect transistor for driving load has conventionally been known. As an example of the double-diffusion field effect transistor, there has been adopted a semiconductor device such as shown in FIG. 13 (see Japanese Laid-Open Patent Publication “Tokkai” No. 2003-174166). FIG. 13 is a sectional view of a semiconductor device 500 which includes an N-type semiconductor substrate 1, an N-type drift region 2 disposed on the semiconductor substrate 1, a P-type base region 5 disposed on the drift region 2, a gate electrode 4, a source electrode 9, a drain electrode 10, and an interlayer insulating film 8.
The gate electrode 4 is disposed in a trench 15 which penetrates the base region 5 to reach the drift region 2.
There has been known also a semiconductor device as shown in Japanese Laid-Open Patent Publication “Tokkai” No. 2004-95954, as a double-diffusion field effect transistor. FIG. 14 is a sectional view of the semiconductor device as shown in “Tokkai” No. 2004-95954, wherein a semiconductor device 600 has a P-type region 601 held between an N-type region 603 which corresponds to the drift region on the semiconductor substrate 1, and an N-type region 602 under the base region 5.
It is to be noted that FIGS. 13 and 14 show only two cells, but a practical semiconductor device has several thousands or more cells formed therein.
The conventional technique described in Japanese Laid-Open Patent Publication “Tokkai” No. 2003-174166, however, still has room for improvement in the aspects below.
The semiconductor device 500 adopts a trench gate structure having the gate electrode disposed in the trench 15 which penetrates the base region 5 to reach the drift region 2, so that the ON-resistance per unit area can be lowered. The semiconductor device having a small ON-resistance per unit area allows a large current to flow therethrough per unit area, but this results in generation of a large energy of heat per unit area when any abnormality such as short-circuiting of the load occurs. The semiconductor device is therefore likely to cause thermal fracture.
On the other hand, a semiconductor device 600 as shown in Japanese Laid-Open Patent Publication No. 2004-95954 has a P-type region 601 provided therein, for the purpose of depleting the periphery of the trench 15 having the gate electrode 4 disposed therein, so as to lower parasitic capacitance of the periphery of the trench 15. The P-type region 601 is configured as covering a region below the bottom of the trench 15, and thereby the width of a current path directed from the N-type region 603 to the base region 5 is considerably narrowed by the P-type region 601. This sort of semiconductor device 600 has the width of current path considerably narrowed not only in case of abnormality such as short-circuiting of the load, but also in the normal operation, always showing a large ON-resistance.
Although Japanese Laid-Open Patent Publication “Tokkai” 2004-95954 describes that increase in the ON-resistance ascribable to the P-type region 601 is avoidable because a path for the channel current is ensured as indicated by arrow Y, but it is understood that the ON-resistance increases to a large degree as compared with that of the semiconductor device 500.